Fpga Implementation of Folded Semi-Systolic Fir Filter with Changeable Folding Factor

Tokić, Tefih and Ćirić, V. and Milentijević, Ivan and Vojinović, O. (2002) Fpga Implementation of Folded Semi-Systolic Fir Filter with Changeable Folding Factor. In: Proceedings of the Third Conference on Informatics and Information Technology. Institute of Informatics, Faculty of Natural Sciences and Mathematics, Ss. Cyril and Methodius University in Skopje, Macedonia, Skopje, Macedonia, pp. 21-30. ISBN 9989-668-36-1

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Abstract

The bit-level transformation of the original data flow graph (DFG), for the bit-plane architecture, that provides the successful application of the folding technique with changeable folding is presented at transfer function level. The mathematical path that describes the transformation is given, and implications at the DFG level are discussed. Changeable folding sets are involved with aim to increase the throughput of the folded system reducing the folding factor according to the coefficient length. The folded FIR filter architecture is described in VHDL as a parameterized FIR filtering core and implemented in FPGA technology. The design "tradeoffs" relating on the occupation of the chip resources and achieved throughputs are presented.

Item Type: Book Section
Uncontrolled Keywords: systolic arrays, FIR filtering, folding technique, FPGA
Subjects: International Conference on Informatics and Information Technologies > Computer architectures
International Conference on Informatics and Information Technologies > Computer networks
Depositing User: Vangel Ajanovski
Date Deposited: 28 Oct 2016 00:15
Last Modified: 03 May 2018 09:19
URI: http://eprints.finki.ukim.mk/id/eprint/11294

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