Parity Error Detection in Embedded System

Stojčev, Mile and Stanković, T. (2001) Parity Error Detection in Embedded System. In: Proceedings of the Second Conference on Informatics and Information Technology. Institute of Informatics, Faculty of Natural Sciences and Mathematics, Ss. Cyril and Methodius University in Skopje, Macedonia, Skopje, Macedonia, pp. 293-307. ISBN 9989-668-28-0


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In this article we describe one suitable approach that enables the designer to insert a boundary-scan and built-in-self-test concepts, as typical design for-testability techniques in system-on-chip and multichip module embedded system design, for fault-effects detection. For transient error detection implementation of parity error detection into a 36-bit bus transceiver circuit (32-bit data and four parity bits) is given. The bus transceiver can be implemented as custom or semi-custom integrated circuit in submicron technology and low cost FPGA or CPLD circuit, core within a system-on-a-chip, or glue logic (bridge) within the multichip module.

Item Type: Book Section
Uncontrolled Keywords: embedded systems, parity error detection, bus transceiver
Subjects: International Conference on Informatics and Information Technologies > Computer Systems and Applications
Depositing User: Vangel Ajanovski
Date Deposited: 28 Oct 2016 00:15
Last Modified: 28 Oct 2016 00:15

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