Design for Low-Power Using Multi-Phase and Multifrequency Clocking

Stojčev, Mile and Jovanović, G. (2002) Design for Low-Power Using Multi-Phase and Multifrequency Clocking. In: Proceedings of the Third Conference on Informatics and Information Technology. Institute of Informatics, Faculty of Natural Sciences and Mathematics, Ss. Cyril and Methodius University in Skopje, Macedonia, Skopje, Macedonia, pp. 31-41. ISBN 9989-668-36-1

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Official URL: http://ciit.finki.ukim.mk

Abstract

In this paper we present a frequency multiplier circuit implemented on a 1.2μm CMOS technology using dedicated design methodology, delay oriented design. The circuit converts a square wave signals in both quadrature – in phase, and eight in phase square wave signal. It also multiplies the frequency by two and four. The output frequency of this converter, for 1.2μm CMOS technology, extends from 20MHz to 80MHz. This converter is dedicated for design frequency synthesizer using double loop architecture implemented in embedded instrumentation.

Item Type: Book Section
Uncontrolled Keywords: Low power design, Frequency multiplier, DLL
Subjects: International Conference on Informatics and Information Technologies > Computer architectures
International Conference on Informatics and Information Technologies > Computer networks
Depositing User: Vangel Ajanovski
Date Deposited: 28 Oct 2016 00:15
Last Modified: 03 May 2018 09:24
URI: http://eprints.finki.ukim.mk/id/eprint/11217

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