Folded Bit-Plane Architectures

Milentijević, Ivan and Nikolić, I. and Vojinović, O. and Đirić, V. and Tokić, Tefih (2001) Folded Bit-Plane Architectures. In: Proceedings of the Second Conference on Informatics and Information Technology. Institute of Informatics, Faculty of Natural Sciences and Mathematics, Ss. Cyril and Methodius University in Skopje, Macedonia, Skopje, Macedonia, pp. 282-292. ISBN 9989-668-28-0

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Abstract

This paper describes the application of folding technique to the bitplane systolic FIR filter architecture. We present two additional transformations of original DFG (Data Flow Graph) that enable the application of folding technique and the synthesis of two different folded architectures. One without latches in carry and sum paths suitable for the filtering with small number of coefficients and the other with greater hardware complexity which is fully pipelined.

Item Type: Book Section
Uncontrolled Keywords: systolic arrays, folding technique, FIR filtering
Subjects: International Conference on Informatics and Information Technologies > Computer Systems and Applications
Depositing User: Vangel Ajanovski
Date Deposited: 28 Oct 2016 00:15
Last Modified: 28 Oct 2016 00:15
URI: http://eprints.finki.ukim.mk/id/eprint/11132

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